The present invention relates to a circuit for generating and checking parity of data words in a multiple bit system.
Often in complex circuitry there is a complex bus timing that demands the generation of parity from different circuits and at different times in the bus cycle. A parity checker may also be required to generate parity at yet another time in a cycle so that the value generated can be compared to an already existing parity. The use of three or more circuits to accomplish the above would ordinarily comsume too much power and use too much silicon area in the case where VLSI applications are involved. Moreover, totally static or totally precharge/discharge generators would simply not meet the speed requirements of present day bus cycles.
Accordingly, an object of the present invention is to provide an improved parity generator/checker circuit. More particularly, it is an object of the present invention to provide a parity generator/checker circuit capable of both checking and generating parity at different times in a bus cycle.